Assembly challenges in developing 3D IC package with ultra high yield and high reliability


As the size and complexity of the designs grows larger, Field Programmable Gate Array (FPGA) based design solutions are becoming more dominant in system designs due to their ability to offer higher logic capacity and more on chip resources. FPGA based design solutions that offer higher capacity and higher bandwidth with low latency and power can provide system level functionality similar to Application Specific Integrated Circuits (ASICs). Stacked die technology enables high bandwidth connectivity between the multiple die by providing significantly large number of connection via microbumps. This interposer based die stacking approach provides low power and latency, but also adds manufacturing complexity. Any assembly process technology is viable only if it is manufacturable with high yields. This paper discusses key challenges observed during manufacturing of 28nm 3DIC products with CoWoS™ (Chip-On-Wafer-On-Substrate) process. During the initial product ramp stage, most of the failures observed were related to interposer level assembly process. Common failure modes were ubump opens, interposer metal line opens and shorts, interposer metal line shorts and TSV to C4 opens. Specific isolation patterns were developed to isolate the interconnect failure to single ubump. After identifying the ubump, the failure was verified with failure analysis. The failure was then mapped on the interposer wafer and analyzed for any inline process deviations. With such close loop feedback process, this problem was resolved quickly to provide very stable and high yielding interconnection process. Another unique failure mode observed during assembly was transistor damage caused during 3DIC assembly. In order to identify the root cause and isolate the problem, different assembly process splits and process corner studies were performed. A C4 probe card was designed to provide an intermediate test point at a major process loop after wafer level die assembly and before flip chip assembly of the stacked die on the organic package. The results of the intermediate probing suggested that multiple process steps could be contributing to this type of failure mode. Failure isolation was performed by post processing of final test data. With specialized isolation patterns, the failure locations were mapped on the interposer wafers and the FPGA wafer. Results suggested that wafer fab process changes did not have an impact on the failure mode and transistor defects were introduced during integration and assembly of FPGA die on the interposer wafer. Series of assembly improvements implemented in the assembly process will be discussed in the paper. The process improvement qualification was completed by subjecting the parts to temperature cycling and high temperature storage (HTS) tests. Extended temperature cycling tests were performed and the parts were subjected to Level 4 preconditioning followed by 1500 cycles of -55°C to 125°C temperature cycle condition. Evaluation units were also subjected to 4000 hours of HTS. All the parts successfully passed the extended reliability evaluations.


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